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NCP5359 Gate Driver for Notebook Power Systems
The NCP5359 is a high performance dual MOSFET gate driver optimized to drive the gates of both high-side and low-side power MOSFETs in a synchronous buck converter. Each of the drivers can drive up to 3 nF load with a 25 ns propagation delay and 20 ns transition time. Adaptive nonoverlap and power saving operation circuit can provide a low switching loss and high efficiency solution for notebook and desktop systems. A high floating top driver design can accommodate VBST voltage as high as 35 V, with transient voltages as high as 35 V. Bidirectional EN pin can provide a fault signal to controller when the gate driver fault detect under OVP, UVLO occur. Also, an undervoltage lockout function guarantees the outputs are low when supply voltage is low, and a thermal shutdown function provides the IC with overtemperature protection.
Features http://onsemi.com MARKING DIAGRAMS
8 8 1 SOIC-8 D SUFFIX CASE 751 N5359 ALYW G
1
DFN-10 MN SUFFIX CASE 485C A L Y W G
N5359 ALYW G
* * * * * * * * * *
Faster Rise and Fall Times Thermal Shutdown Protection Adaptive Nonoverlap Circuit Floating Top Driver Accommodates Boost Voltages of up to 35 V Output Disable Control Turns Off Both MOSFETs Complies with VRM 11.1 Specifications Undervoltage Lockout Power Saving Operation Under Light Load Conditions Thermally Enhanced Package These are Pb-Free Devices
= Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
PIN CONNECTIONS
BST PWM EN VCC 1 BST PWM EN VCC VCC (Top View) 10 DRVH SW GND GND DRVL 1 8 DRVH SW GND DRVL
Typical Applications
* Power Solutions for Desktop and Notebook Systems
ORDERING INFORMATION
Device NCP5359DR2G NCP5359MNR2G Package SOIC-8 (Pb-Free) DFN-10 (Pb-Free) Shipping 2500 Tape & Reel 3000 Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specification Brochure, BRD8011/D.
(c) Semiconductor Components Industries, LLC, 2009
February, 2009 - Rev. 3
1
Publication Order Number: NCP5359/D
NCP5359
BST VCC
ChipEN Level Shift and Driver
DRVH
EN
Fault
PWM
DRVH Comparator PWM > 2.2 V = 1, Else = 0
Falling Edge Delay
1.0 V UVLO Thermal Shutdown FPWM Comparator 0.8 V < PWM < 2.2 V = 1, Else 0 EN Pre -Over voltage Pre-OV 2 V/1 V Falling Edge Delay R Q S Q Driver Pre-OV + - Fault ChipEN
SW 1 mV l +
+ -
ChipEN
GND
VCC DRVL
Figure 1. Internal Block Diagram
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+ - + l SW l + GND
NCP5359
4 V to 15 V *Option BST PWM EN PWM EN VCC 10 V to 13.2 V VCC DRVH SW GND GND DRVL
VOUT
Figure 2. Typical Application
PIN DESCRIPTION
SOIC-8 1 2 DFN10 1 2 Symbol BST PWM Description Upper MOSFET Floating Bootstrap Supply Pin PWM Input Pin When PWM voltage is higher than 2.2 V, DRVH will set to 1 and DRVL set to 0 When PWM voltage is lower than 0.8 V, DRVL will set to 1 and DRVH set to 0 When 0.8 V < PWM < 2.2 V and SW < 0, DRVL will set to 1 When 0.8 V < PWM < 2.2 V and SW > 0, DRVL will set to 0 Enable Pin When OVP, TSD or UVLO has happened, the gate driver will pull the pin to low Connect to Input Power Supply 10 V to 13.2 V Low Side Gate Drive Output Ground Pin Switch Node Pin High Side Gate Drive Output
3 4 5 6 7 8
3 4, 5 6 7, 8 9 10
EN VCC DRVL GND SW DRVH
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NCP5359
MAXIMUM RATINGS
Rating Thermal Characteristics, Plastic Package Thermal Resistance Junction-to-Air Operating Junction Temperature Range Operating Ambient Temperature Range Storage Temperature Range Moisture Sensitivity Level SOIC-8 DFN10 SOIC-8 DFN10 Symbol RqJA Value 178 45 0 to +150 0 to +85 - 55 to +150 3 1 Unit C/W
TJ TA Tstg MSL
C C C -
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
MAXIMUM RATINGS
Pin Symbol Vcc BST Pin Name Main Supply Voltage Input Bootstrap Supply voltage VMAX 15 V 35 V wrt / GND 40 V 50 ns wrt / GND 15V wrt / SW 35 V wrt / GND 40 V 50 ns wrt / GND BST + 0.3 V 35 V 50 ns wrt / GND 15V wrt / SW Vcc + 0.3 V 6V 6V 0V VMIN -0.3 V -0.3 V
SW DRVH
Switching Node (Bootstrap Supply Return) High Side Driver Output
-1 VDC -10 V (200 ns) (Note 4) -0.3 V -2 V (200 ns) -0.3 V -5 V (200 ns) -0.3 V -0.3 V 0V
DRVL PWM EN GND
Low Side Driver Output DRVH and DRVL Control Input Enable Pin Ground
1. Latchup Current Maximum Rating: 100 mA per JEDEC standard: JESD78. 2. Moisture Sensitivity Level (MSL): 1&3 per IPC/JEDEC standard: J-STD-020A. 3. The maximum package power dissipation limit must not be exceeded.
PD +
4. Switching node negative voltage is -5 V ( 200 ns) at PSI mode. NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
TJ(max) * TA RqJA
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NCP5359
ELECTRICAL CHARACTERISTICS (VCC = 12 V, TA = 0C to +85C, VEN = 5 V unless otherwise noted)
Characteristics Supply Voltage VCC Operating Voltage Power ON Reset threshold Supply Current VCC Quiescent Supply Current in Normal Operation VCC Standby Current BST Quiescent Supply Current in Normal Operation BST Standby Current Undervoltage Lockout VCC Start Threshold VCC UVLO Hysteresis Output Overvoltage Trip Threshold at Startup EN Input Input Voltage High Input Voltage Low Hysteresis (Note 5) Enable Pin Sink Current Propagation Delay Time (Note 5) PWM Input DRVH Comparator Drop Threshold PWM Input Self Bias Voltage DRVL Comparator Rise Threshold Input Current High Side Driver Output Resistance, Sourcing Output Resistance, Sinking Transition Time (Note 7) Propagation Delay (Notes 5 & 6) Low Side Driver Output Resistance, Sourcing Output Resistance, Sinking Transition Time (Note 7) Propagation Delay (Notes 5 & 6) Negative Current Detector Threshold Thermal Shutdown Thermal Shutdown Thermal Shutdown Hysteresis Tsd Tsdhys (Note 7) (Note 7) 150 170 20 C C RH_BG RL_BG trDRVL tfDRVL tpdhDRVL tpdlDRVL VNCDT SW = GND SW = VCC CLOAD = 3 nF CLOAD = 3 nF Driving High, CLOAD = 3 nF Driving Low, CLOAD = 3 nF (Note 7) 10 8.0 -1.0 2.0 1.0 16 11 3.5 2.5 25 15 35 30 mV ns W W ns RH_TG RL_TG trDRVH tfDRVH tpdhDRVH tpdlDRVH VBST - VSW = 12 V VBST - VSW = 12 V CLOAD = 3 nF, VBST - VSW = 12 V CLOAD = 3 nF, VBST - VSW = 12 V Driving High, CLOAD = 3 nF Driving Low, CLOAD = 3 nF 10 8.0 2.0 1.0 16 11 3.5 2.5 25 15 35 30 ns W W ns VTH_DRVH VPWM VTH_DRVL IPWM PWM = 0 V, EN = GND 30 2.2 1.4 1.5 1.6 0.8 V V V mA VEN_HI VEN_LOW VEN_HYS IEN_SINK tpdhEN tpdlEN VCC = 5.5 V 5.0 20 20 60 60 500 2.0 1.0 V V mV mA ns ns VCCTH VCCHYS OVPSU Power Startup time, VCC > 9 V. (Without trimming) 1.8 8.2 8.7 1.0 2.0 9.5 V V V IVCC_NORM IVCC_SBC IBST1_normal IBST2_normal IBST1_SD IBST2_SD EN = 5 V, PWM = OSC, FSW = 100 k CLOAD = 0 p EN = GND; No switching PWM = +5 V, SW = 0 V PWM = GND, SW = 0 V PWM = +5 V PWM = GND 2.0 0.5 1.0 1.0 0.25 0.25 5.0 1.0 1.8 1.8 mA mA mA mA VCC VPOR 10 2.8 13.2 V V Symbol Test Conditions Min Typ Max Units
5. Guaranteed by design; not tested in production . 6. For propagation delays, "tpdh" refers to the specified signal going high "tpdl" refers to it going low. 7. Design guaranteed.
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NCP5359
Table 1. DECODER TRUTH TABLE
PWM Input Greater than 2.2 V Greater than 0.8 V, but less than 2.2 V Greater than 0.8 V, but less than 2.2 V Less than 0.8 V ZCD X High (current through MOSFET is greater than 0) Low (current through MOSFET is less than 0) X DRVL Low High Low High DRVH High Low Low Low
IN DRVL
tpdlDRVL 90% 2V
tfDRVL 90% 10% tpdhDRVH trDRVH 90% tpdlDRVH 90% 2V 10% tpdhDRVL tfDRVH 10% trDRVL
DRVH-SW
10%
SW
Figure 3.
PWM
DRVH-SW
DRVL
IL
Figure 4. Timing Diagram
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NCP5359
APPLICATION INFORMATION The NCP5359 gate driver is a single phase MOSFET driver designed for driving two N-channel MOSFETs in a synchronous buck converter topology. This driver is compatible with the NCP3418B gate drive. This gate drives operation is similar with the NCP3418B, but has two additional new features: Bidirection fault detection and multilevel PWM input. When the gate driver works with ON Semiconductor's NCP5392 controller, it can provide a difference output logic status through multi-level PWM input. For this new feature, higher efficiency can be provided. For the bidirection fault detection function, it is used to provide a driver state information to other gate drivers and controller in a multiphase buck converter. e.g overvoltage protection (OVP) function at startup, thermal shutdown and undervoltage lockout (UVLO). This feature can provide an additional protection function for the multi-phase system when the fault condition occurs in one channel. With this additional feature, converter overall system will be more reliable and safe.
Enable Pin Power ON reset
Power on reset feature is used to protect a gate driver avoid abnormal status driving the startup condition. When the initial soft-start voltage is higher than 3.2 V, the gate driver will monitor the switching node SW pin. If SW pin high than 1.9 V, bottom gate will be force to high for discharge the output capacitor. The fault mode will be latch and EN pin will force to be low, unless the driver is recycle. When input voltage is higher than 9 V, the gate driver will normal operation, top gate driver DRVH and bottom gate driver will follow the PWM signal decode to a status.
Adaptive Nonoverlap
The bidirection enable pin is connected with an open drain MOSFET. This pin is controlled by internal or external signal. There are three conditions will be triggered: 1. The voltage at SWN pin is higher than preset voltage at power startup. 2. The controller hits the UVLO at VCC pin. 3. The controller hits the thermal shutdown. When the internal fault has been detected, EN pin will be pull low. In this case, the drive output DRVH and DRVL will be forced low, until the fault mode remove then restart automatic.
Undervoltage Lockout
The nonoverlap dead time control is used to avoid the shoot through damage the power MOSFETs. When the PWM signal pull high, DRVL will go low after a propagation delay, the controller will monitors the switching node (SWN) pin voltage and the gate voltage of the MOSFET to know the status of the MOSFET. When the low side MOSFET status is off an internal timer will delay turn on of the high-side MOSFET. When the PWM pull low, gate DRVH will go low after the propagation delay (tpd DRVH). The time to turn off the high side MOSFET is depending on the total gate charge of the high-side MOSFET. A timer will be triggered once the high side MOSFET is turn off to delay the turn on the low-side MOSFET.
Layout Guidelines
The DRVH and DRVL are held low until VCC reaches 9 V during startup. The PWM signals will control the gate status when VCC threshold is exceeded. If VCC decreases to 3.2 V below the threshold, the output gate will be forced low until input voltage VCC rises above the startup threshold.
Layout is very important thing for design a DC-DC converter. Bootstrap capacitor and VCC capacitor are most critical items, it should be placed as close as to the driver IC. Another item is using a GND plane. Ground plane can provide a good return path for gate drives for reducing the ground noise. Therefore GND pin should be directly connected to the ground plane and close to the low-side MOSFET source pin. Also, the gate drive trace should be considered. The gate drives has a high di/dt when switching, therefore a minimized gate drives trace can reduce the di/dv, raise and fall time for reduce the switching loss.
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NCP5359
PACKAGE DIMENSIONS
DFN10, 3x3 MN SUFFIX CASE 485C-01 ISSUE B
D A B L1
EDGE OF PACKAGE NOTES: 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM FROM TERMINAL. 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. 5. TERMINAL b MAY HAVE MOLD COMPOUND MATERIAL ALONG SIDE EDGE. MOLD FLASHING MAY NOT EXCEED 30 MICRONS ONTO BOTTOM SURFACE OF TERMINAL b. 6. DETAILS A AND B SHOW OPTIONAL VIEWS FOR END OF TERMINAL LEAD AT EDGE OF PACKAGE. DIM A A1 A3 b D D2 E E2 e K L L1 MILLIMETERS MIN MAX 0.80 1.00 0.00 0.05 0.20 REF 0.18 0.30 3.00 BSC 2.40 2.60 3.00 BSC 1.70 1.90 0.50 BSC 0.19 TYP 0.35 0.45 0.00 0.03
PIN 1 REFERENCE 2X 2X
0.15 C
0.15 C
0.10 C
10X
DETAIL B
(A3) A A1
SEATING PLANE
0.08 C SIDE VIEW D2
10X
A1
DETAIL A 5
C
L
e
1
10X
K
E2
10 10X
6
b BOTTOM VIEW
0.10 C A B 0.05 C
NOTE 3
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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EEE EEE EEE
10X
CCCC CCCC CCCC
E
DETAIL A Bottom View (Optional)
EXPOSED Cu MOLD CMPD
TOP VIEW
A3
DETAIL B Side View (Optional)
SOLDERING FOOTPRINT*
2.6016
2.1746
1.8508
3.3048
0.5651
0.3008
10X
0.5000 PITCH
DIMENSIONS: MILLIMETERS
NCP5359
PACKAGE DIMENSIONS
SOIC-8 CASE 751-07 ISSUE AJ
-X-
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. 751-01 THRU 751-06 ARE OBSOLETE. NEW STANDARD IS 751-07. MILLIMETERS MIN MAX 4.80 5.00 3.80 4.00 1.35 1.75 0.33 0.51 1.27 BSC 0.10 0.25 0.19 0.25 0.40 1.27 0_ 8_ 0.25 0.50 5.80 6.20 INCHES MIN MAX 0.189 0.197 0.150 0.157 0.053 0.069 0.013 0.020 0.050 BSC 0.004 0.010 0.007 0.010 0.016 0.050 0_ 8_ 0.010 0.020 0.228 0.244
A
8 5
B
1
S
4
0.25 (0.010)
M
Y
M
-Y- G
K
C -Z- H D 0.25 (0.010)
M SEATING PLANE
N
X 45 _
0.10 (0.004)
M
J
ZY
S
X
S
DIM A B C D G H J K M N S
SOLDERING FOOTPRINT*
1.52 0.060
7.0 0.275
4.0 0.155
0.6 0.024
1.270 0.050
SCALE 6:1 mm inches
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
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NCP5359/D

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